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Renesas Electronics /R7FA6T2BD /ADC_B /ADCLKCR

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Interpret as ADCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)CLKSEL 0 (000)DIVR

CLKSEL=00, DIVR=000

Description

A/D Conversion Clock Control Register

Fields

CLKSEL

ADCLK Clock Source Select

0 (00): Peripheral Module Clock C (PCLKC)

1 (01): Setting prohibited

1 (01): GPT clock (GPTCLK)

2 (10): Peripheral Module Clock A (PCLKA)
DIVR

Clock Division Ratio Select

0 (000): 1/1

1 (001): 1/2

2 (010): 1/3

3 (011): 1/4

4 (100): 1/5

5 (101): 1/6

6 (110): 1/7

7 (111): 1/8

Links

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Register License

This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all applicable laws, including copyright laws.

THIS SOFTWARE IS PROVIDED “AS IS” AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of this software. By using this software, you agree to the additional terms and conditions found by accessing the following link: http://www.renesas.com/disclaimer

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data